A display device in which a display element is arranged for every pixel and that displays an image by ON/OFF controlling the each display element will be described below.
FIG. 1 shows a circuit diagram of one display element. As the display element, ones that use a liquid crystal, a light emitting device and the like are known. Here, as an example, the display element using liquid crystal will be explained. One of data (source) lines, one of gate lines, a transistor (TFT 200 (TFT: Thin Film Transistor)), a retention capacitor (Cs 300), and a pixel electrode A are provided for one display element (CLC 200 (CLC: Liquid Crystal Capacitor)) In the case of the liquid crystal display device, the pixel section is considered as a capacitor (CLC) in terms of an equivalent circuit.
A gate electrode (G) of the TFT 200 is connected to a gate line 2-2, a source region (S) thereof is connected to a data line 1-1, and a drain region (D) thereof is connected to a pixel electrode 10. One end of the Cs 300 is connected to the drain region (D) of the TFT 200 through the pixel electrode 10, and the other end thereof is connected to a gate line 2-2 of a gate line 2-1 of the previous stage.
It should be noted that the Cs 300 is not necessarily provided. Since the CLC 100 also is a capacitor, the CLC 100 alone may be enough for maintaining the voltage, depending on an embodiment of the pixel (the CLC 100) and the TFT 200. Moreover, the TFT 200 can be either a p-channel type or an n-channel type.
Regarding the display device thus configured, an operation when displaying an image will be explained below.
When a signal voltage is supplied to the gate line 2-2 at certain timing, electric potential of the gate electrode (G) of the TFT 200 varies and a gate voltage varies. Thereby, the TFT 200 becomes in a conductive state. While TFT 200 is maintained in the conductive state, a signal voltage is supplied to the data line 1-1 at certain timing. Then, electric potential of the drain electrode (D) of the TFT 200 that is conductive varies. Thus, electric potential of the pixel electrode 10 connected to the Cs 300 and the CLC 100 varies, and the Cs 300 and the CLC 100 are charged. A shutter is switched by the CLC 100 being charged, and optical transmittance varies. Thereby, display in this display pixel is performed. Here, even if the supply of the signal to the data line 1-1 and the gate line 2-2 is stopped before the liquid crystal shutter is completely switched, the liquid crystal shutter can be switched by a voltage retained by the Cs 300. It is therefore possible to supply the signal voltage to a data line and a gate line of the next pixel, without waiting until the liquid crystal shutter is completely switched. It should be noted that the other end of the Cs 300 (an electrode on the opposite side of the drain region (D)) is connected to the gate line 2-1 that is switched at the previous step (namely, of a pixel whose switching is completed). Therefore, the other end of the Cs 300 is always connected to the gate line 2-1 supply of the signal to whom is stopped, and thus it does not cause interference. Moreover, since the other end of the Cs 300 is connected to the gate line 2-1 of the previous stage, it is possible to decrease unnecessary interconnections.
The above-mentioned method where the switching transistor (TFT) is provided for each pixel is called an active matrix type. The active-matrix type display device is described, for example, in Japanese Laid-Open Patent Application No. 2006-91089, Japanese Laid-Open Patent Application No. 2006-184853, Japanese Laid-Open Patent Application No. 2002-328617, and Japanese Laid-Open Patent Application No. 2002-31817.
In the active-matrix type display device, how precise the display pixel (liquid crystal in the above-mentioned example) can be switched is important. Therefore, precision of the transistor that switches an electrical state of the display pixel determines gradation ability of the display device. Moreover, not only the gradation but also power consumption, an image quality and the like are greatly influenced by the performance of the switching transistor. For example, if a leakage current is caused in the transistor when the signal voltage is not supplied to the gate line and the data line, electric charges leak from the charged retention capacitor. Existence of the leakage current means that light is not completely cut off, which causes deterioration of the gradation ability. Moreover, in that case, the voltage for switching the display pixel also varies. Furthermore, in order to prevent this, it is necessary to input the same signal again with a short interval, which consumes excessive electric power. Moreover, charging need to be performed generously in consideration of the leakage current, which makes a charging time for one display element longer. As a result, it becomes necessary to increase an interval of switching the image for each frame, and for example, many missing scenes are caused in video. Therefore, a technique which can suppress the off-leakage current in the switching transistor in the OFF state is desired.
As the switching transistor used in the display element of the active-matrix type display device, a field-effect type transistor using a polycrystalline semiconductor thin film (hereinafter referred to as p-TFT) is known. The p-TFT is advantageous in that field effect mobility is large, as compared with a TFT using an amorphous semiconductor thin film (hereinafter referred to as a-TFT).
In order to suppress the off-leakage current in the p-TFT, it may be considered to employ a Lightly Doped Drain (LDD) structure, for example. This technique is a measure against the so-called short channel effect. By changing doping concentration with respect to a channel, an electric field applied to the channel layer is controlled such that the off-leakage current is suppressed. A technique employing the LDD structure is described, for example, in Japanese Laid-Open Patent Application No. 2005-64123 and Japanese Laid-Open Patent Application No. H09-129891.
As another technique for suppressing the off-leakage current, it may be considered to devise a structure of a gate electrode. By devising the structure of the gate electrode, an electric field applied to the semiconductor layer can be controlled. Such a transistor is described, for example, in Japanese Laid-Open Patent Application No. H07-321324, Japanese Laid-Open Patent Application No. 2006-100404, IEEE TRANSACTIONS ON ELECTRON DEVICES VOL. 39, NO. 4, p. 916 (Conventional Technique 1), IEEE ELECTRON DEVICE LETTERS, VOL. 22, NO. 10, p. 472 (Conventional Technique 2) and PHYSICAL REVIEW LETTERS VOL. 93, No. 19, p. 196805 (Conventional Technique 3).
In the Conventional Technique 1 among them, a transistor in which a sub-gate for controlling source/drain regions is provided on a main gate is described. In the Conventional Technique 1, it is described that the sub-gate is controlled by a sub-gate voltage Vs.
In the Conventional Technique 2, it is described that a metal that is electrically floating (being not connected/being not controlled) is provided as the sub-gate in the transistor. According to the Conventional Technique 2, the sub-gate plays a role of a doping mask, and impurity concentration in the channel layer immediately under the sub-gate is lowered. Thereby, the leakage current is suppressed as in the case of the LDD structure.
In the Conventional Technique 3, it is described that a gate electrode is divided and controlled by the same electric potential.
By the way, a transistor other than the p-TFT is also known as the transistor for the display device. For example, a transistor other than the p-TFT includes a transistor (hereinafter referred to as a CNT-FET) that uses carbon nanotube (CNT) as the semiconductor layer.
The CNT-FET has more merits than the p-TFT in that a high-temperature treatment process is not required in the manufacturing processes, a huge manufacturing apparatus is not necessary and so on. In a case of manufacturing the p-TFT, an annealing treatment that requires a high processing temperature is necessary during the manufacturing processes. Therefore, it is difficult to use low heat resistance material. Moreover, since it is basically manufactured by a vacuum apparatus such as a sputtering apparatus, a large-scale and expensive vacuum apparatus is necessary for manufacturing a large area display device. On the other hand, the CNT-FET can be manufactured by a coating method, a printing method and the like, because CNT can be dissolved in a solution. Therefore, a huge vacuum apparatus is not required in manufacturing the CNT-FET and thus the manufacturing cost can be greatly suppressed. Moreover, since a high-temperature treatment is not necessary, low heat resistance material such as a plastic substrate can be used as a base substrate, which makes it possible to manufacture a flexible display device.
FIG. 2 is a schematic cross-sectional view showing an example of a typical CNT-FET. As shown in FIG. 2, the CNT-FET has a gate electrode 105, a source electrode 103, a drain electrode 104, a semiconductor layer 107 and a pixel electrode 110 that are formed on a substrate 109. The gate electrode 105 is formed in contact with the substrate 109 and is covered by a gate insulating film 112. The semiconductor layer 107 is formed on the gate insulating film 112 so as to face the gate electrode 105 across the gate insulating film 112. The semiconductor layer 107 is a layer including CNT. The source electrode 103 and the drain electrode 104 are formed on both ends of the semiconductor layer 107. The source electrode 103 and the drain electrode 104 are usually metal electrodes. A protection film 111 is so provided as to cover the source electrode 103, the drain electrode 104 and the semiconductor layer 107. Moreover, the pixel electrode 110 is formed on a part of the protection film 111. The pixel electrode 110 is connected to the drain electrode 104 through an aperture provided in a part of the protection film 111.
The CNT-FET is manufactured through the following processes (1) to (5). (1) Making a surface of a substrate insulating. If a substrate is insulating, it can be used as it is. (2) Forming the gate electrode 105. (3) Forming the gate insulating film 112. (4) Forming electrodes to be the source electrode 103 and the drain electrode 104. (5) Printing and coating material to be the semiconductor layer 107. The above is the most fundamental processes. As an alternative method, the order of (1) to (5) may be changed to an order of (1), (5), (4), (3) and (2). Moreover, an order of (1), (2), (3), (5) and (4) also is possible. In either case, the protection film 111 and the like are formed at the end.
In the CNT-FET shown in FIG. 2, the gate electrode 105 and the semiconductor layer 107 form a capacitor across the gate insulating film 112. By controlling a voltage of the gate electrode 105, it is possible to change a voltage (electric potential, potential) of a part of the semiconductor layer 107. By changing the electric potential of the part of the semiconductor layer 107, it is possible to control electric charge density or energy barrier in the semiconductor layer 107. That is to say, the amount of current flowing through the semiconductor layer 107 can be controlled by controlling the gate voltage. This is the same operation as in the case of a typical silicon-type field-effect transistor.
Such a CNT-FET is described, for example, in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, and NO. 7, p. 1402 (Conventional Technique 4).
The LDD structure is useful for such a transistor as the p-TFT using a silicon film as the semiconductor layer wherein the doping method is established. However, it is difficult to apply the LDD structure to material (for example, CNT-FET) wherein the doping method is not yet established.
Moreover, even if the structure of the gate electrode of a transistor other than the p-TFT is devised as in the above-mentioned document, the leakage current is not necessarily suppressed. For example, even if the structure in which a plurality of gate electrodes are stacked as in the Conventional Technique 2 is applied to the CNT-FET, the leakage current is not necessarily suppressed. In fact, according to the Conventional Technique 4 whose structure is similar to that of the Conventional Technique 1, it is described that the leakage current clearly exists when the gate voltage is positive.
The reason why the conventional sub-gate structure is not effective for the leakage current in the transistor other than the p-TFT is considered to be that there are different principles of the leakage current as compared with the case of the p-TFT. In the case of the CNT-FET, for example, charge transfer in a Schottky junction portion between the semiconductor layer and the drain electrode is considered to the cause of the leakage current. In a case of a p-type CNT-FET, holes (majority carriers) are injected from the source side. Ideally, when the gate voltage is positive, a potential of the channel in the gate region rises and hence the current is prevented. In fact, however, when the gate voltage is positive, electrons (minority carriers) are injected from the drain side, which causes the leakage current. In the case of the CNT-FET, influence of the Schottky junction portion on the leakage current is larger, because the Schottky barrier for the minority carriers on the drain side is not so high and the Schottky barrier is lowered by the gate voltage at the time of the OFF operation. Incidentally, the reason why the Schottky barrier of the CNT is small is that a band gap of the CNT is small (for example, in a case where a diameter of CNT is 0.7 to 2 nm, the band gap is 0.4-1.2 eV). The same applies to a case of an n-type CNT-FET, wherein respective carriers are replaced complimentarily.
It is therefore desired to achieve a technique that can suppress the leakage current caused by the Schottky junction portion.
In the display device, it is necessary to ensure an effective area of the pixel section. For example, when the sub-gate is controlled electrically independently as described in the Conventional Technique 2, the voltage applied to the channel layer may be effectively controlled. In this case, however, an interconnection for controlling the sub-gate is necessary in addition to an interconnection connected to a main gate line. Due to this interconnection for controlling the sub-gate, the effective area of the pixel section is decreased. The decrease in the effective pixel area means reduction in brightness ability.
It is therefore desired to achieve a technique that can suppress the leakage current without decreasing the effective pixel area.